주문형 FPGA/ASSP RTL 디자인 해 드립니다.

FPGA / ASSP Logic Design ( RTL Design & Verification )

주문형 FPGA/SOC Board Design

Design 영역 

1.  Intreface Bus Design

    - Ethernet/I2C/SPI/ADC/DAC/ PCI Express/SOC IF (AXI) etc.

2. IP High Speed Serdes

3. 메모리 및 비메모리 테스트 Sub Block

  - ALPG (Pattern Generator) / Vector Generator.

  - DSP(Digital Signal Processing)  Engine Sequence Generator

  - Timing Generator @pS Resolution.

4. DSP(Digital Signal Prcessing) Chip Sub Block

   - RISC Engine

   - ADC/DAC Mixed Signal Interface 

   - Macro Block : ALU/MAC/Barrel Shift/ROM/SRAM

Design Tool

1. Xilinx/Altera Design Tool ( Vivado/Quartus/Modelsim..)

2. Cadence OrCAD/PSpice

3. Verilog HDL